Auxiliary digital data extractor in a television

ABSTRACT

An auxiliary digital data extractor in a television receiver includes a source of a composite video signal. The composite video signal includes an auxiliary digital data component which is either a first frame code having a predetermined number of bits and auxiliary data in a first format, or a second frame code having the same number of bits and auxiliary data in a second format. A frame code detector is coupled to the composite video signal source. The frame code detector is responsive to one subset of the frame code bits to detect the first frame code and to a different subset of frame code bits to detect the second frame code. An auxiliary data utilization circuit is coupled to the composite video signal source and the frame code detector. The auxiliary data utilization circuit receives auxiliary data in the either first format when the first frame code is detected or the second format when the second frame code is detected.

The present invention relates to a television receiver including asystem for identifying and extracting auxiliary digital data, having oneof a plurality of formats, inserted in the vertical blanking interval ofa television video signal.

Currently, auxiliary data, such as, for example, closed captioninginformation and extended data service (XDS) information, is transmittedin digital form during the vertical blanking interval of standardtelevision signals. The closed captioning information represents theclosed caption characters, and XDS information includes a variety ofauxiliary data. This information is inserted in known locations in thevertical blanking interval of the television video signal and formattedin a known manner. In the NTSC television signal in the United States,line 21 in field 1 is reserved for closed captioning information, andline 21 of field 2 is reserved for XDS information.

Referring to FIG. 1, the closed captioning signal is illustrated in thesecond waveform from the top, labeled CC SIG. This signal includes afirst interval of 10.5 microseconds (μs) in which the signal remainsnominally at 0 IRE amplitude. This is followed by a clock run-ininterval of 14 μs containing seven cycles of a 500 kHz sine wave clocksignal having a peak-to-peak amplitude which is the same as the closedcaptioning data, which follows. The peak-to-peak amplitude is nominally50 IRE. The run-in interval is followed by a 3 μs period of 0 IREsignal. After the 3 μs 0 IRE signal interval, a start bit of 2 μsduration occurs, followed by 16 data bit intervals, each also of 2 μsduration, in which data is transmitted in a non-return-to-zero (NRZ)format. In this manner, two bytes of closed captioning information istransmitted. A closed captioning processor in a receiver extracts theclosed captioning data from its location in the vertical blankinginterval and displays that information on the television display device.

Digital auxiliary information other than closed captioning and XDSinformation may also be transmitted in the vertical blanking interval,using the same format, for example, television program schedulinginformation. A scheduling service has been provided by Star-sightcompany in which scheduling information was transmitted in the verticalblanking interval of the video signal, using the same format as theclosed caption information. A scheduling processor in a receiverextracts the scheduling data from its location in the vertical blankinginterval and displays that information, allowing the viewer to make TVprogram selections based on the displayed scheduling data. Recently,however, another format for auxiliary digital data, specifically TVprogram scheduling data, has been proposed by Gemstar company.

No location in the vertical blanking interval has been reserved for theStar-sight or Gemstar scheduling information. Thus, differentbroadcasters are free to include it in any location in the verticalblanking interval, except those locations (lines 21 in fields 1 and 2)reserved for closed captioning information and XDS information. Also,data transmitted in the proposed Gemstar system, may at times be in theclosed caption format, described above, and at other times be in a newlyproposed format, termed the Gemstar format in the remainder of thisapplication.

The Gemstar format signal is illustrated in FIG. 1 as the third waveformfrom the top, labeled GS SIG. A Gemstar format line in the verticalblanking interval also starts with 10.5 μs of nominally 0 IRE signal.But that interval is followed by only 5 cycles of a 500 kHz, nominally50 IRE peak-to-peak, sine wave run-in clock signal. The run-in clocksignal is immediately followed by a digital nine bit frame identifyingcode having the predetermined value of 011101101. Each bit in the framecode takes 1 μs, and is in NRZ format. The frame code is immediatelyfollowed by 32 data bits, each also taking 1 μs, in NRZ format. In thismanner four bytes of scheduling data is transmitted in the closedcaptioning location in the vertical blanking interval. Again, ascheduling processor in the receiver extracts the scheduling data fromits location in the vertical blanking interval and allows the viewer tomake selections based on the scheduling data.

It is desirable to provide an auxiliary information decoder thatreliably decodes multiple auxiliary data formats such as both Gemstarformat data and closed caption data. One problem that can arise whendecoding auxiliary data is that signal noise can cause data to bedecoded incorrectly. For example, noise may cause one or more bits of aframe code to be incorrect. As a result, a frame code detector mayprocess a frame code containing noise-related errors and indicateincorrectly the type of data that exists in a particular portion of atelevision signal. For example, a decoder processing a Gemstar framecode containing erroneous bits may indicate incorrectly that the lineinterval associated with the frame code does not contain Gemstar data.As a result, the decoder may ignore the line interval rather than decodethe data as desired.

In accordance with principles of the present invention, an auxiliarydigital data extractor in a television receiver processes a compositevideo signal including auxiliary digital data components which haveeither a first frame code having a predetermined number of bits andauxiliary data in a first format, or a second frame code having the samenumber of bits and auxiliary data in a second format. A frame codedetector is responsive to one subset of the frame code bits to detectthe first frame code and to a different subset of frame code bits todetect the second frame code. An auxiliary data utilization circuitreceives auxiliary data in the either first format when the first framecode is detected or the second format when the second frame code isdetected.

In accordance with another aspect of the invention, an auxiliaryinformation decoder has a first mode of operation for detecting anyoccurrence of auxiliary information in a signal and a second mode ofoperation for detecting a particular occurrence of auxiliary informationin the signal.

The invention will be explained with reference to the drawing in which:

FIG. 1 is a waveform diagram useful in understanding the operation ofthe present invention;

FIG. 2 is a block diagram of a portion of a television receiverincorporating the present invention;

FIG. 3 is a more detailed block diagram of a vertical blanking intervaldata extractor according to the present invention;

FIG. 4 is a more detailed diagram, partially in block form, andpartially in logic form, illustrating a frame code detector which may beused in a vertical blanking interval data extractor illustrated in FIG.3; and

FIGS. 5 and 6 are more detailed diagrams, partially in block form, andpartially in logic form, illustrating portions of the controller circuitillustrated in FIG. 3.

In the remainder of this application, the term television receiver willrefer to a system capable of receiving and processing a televisionsignal, whether or not that system is capable of rendering the videoimage and the associated audio component. For example, the termtelevision receiver is meant to refer to a standard television receiverwith a display and speakers, and also to refer to the circuitry in avideo cassette recorder (VCR) or set-top cable or satellite box, all ofwhich contain circuitry capable of receiving and processing a televisionsignal, but not of displaying the image or rendering the soundrepresented by that television signal. In addition, in the remainder ofthis application, the auxiliary digital information will refer to eitherclosed caption information or Gemstar scheduling information.

FIG. 2 is a block diagram of a portion of a television receiverincorporating the present invention. In FIG. 2, only those portions ofthe receiver necessary for understanding the operation of the presentinvention are illustrated. One skilled in the art will understand whatother elements are necessary in an operating television receiver, andhow to interconnect those other elements with the elements illustratedin FIG. 2.

In FIG. 2, an input terminal 5 is coupled to a source (not shown) of acomposite video signal. For example, in a standard television receiver,this source may include an antenna or cable connection, RF and IFamplifiers, a detector, and possibly an element for separating the audiocomponent from the video component. As another example, in a standardVCR, the source may include a tape transport mechanism, tape read headand read-back amplifiers. The input terminal 5 is coupled to respectiveinput terminals of a synchronization component separator 10, and a dataslicer 30. A composite synchronization signal output terminal 5 of thesynchronization component separator 10 is coupled to a correspondinginput terminal 5 of a vertical blanking interval (VBI) data extractor20. An output terminal of the data slicer 30 is coupled to a VBI signalinput terminal V of the VBI data extractor. An output terminal of acrystal oscillator 40 is coupled to a clock input terminal (CLK) of theVBI data extractor 20.

A microprocessor 50 is coupled to the VBI data extractor by abidirectional eight-bit data bus. A control output terminal of themicroprocessor 50 is coupled to a corresponding input terminal of theVBI data extractor 20, while an interrupt request output terminal of theVBI data extractor 20 is coupled to a corresponding input terminal ofthe microprocessor 50.

In operation, the composite video signal at input terminal 5 is astandard composite video signal, such as, in the United States, an NTSCcomposite video signal, and contains a video component and asynchronization component (among other components not germane to theunderstanding of the present invention). The synchronization componentseparator 10 operates in a known manner to separate the compositesynchronization component from the composite video signal and supplythat synchronization component to the VBI data extractor 20.

The data slicer 30 produces a serial stream of digital bit signalsrepresenting the composite video signal in a known manner. When thevalue of the composite video signal is greater than the value of a slicelevel, the slicer 30 digital output signal is at a first logic level,and when the value of the video signal is less than the value of theslice level, the digital output signal is at a second logic level. Inthe exemplary embodiment described herein, the first and second logiclevels correspond to logic ‘1’ and logic ‘0’ values, respectively.Referring to FIG. 1, the second waveform from the top CC SIG illustratesthe closed caption format data signal. The run-in signal, consisting ofseven sine wave cycles, has a peak-to-peak value which is the same asthe NRZ data signal which follows. The base value of the sine wave isnominally 0 IRE and the peak value is nominally 50 IRE. Thus, a slicinglevel signal, selected to be midway between the base and peak values, isnominally 25 IRE, as illustrated in the CC SIG waveform. The base andpeak values of the received run-in signal can, of course, vary, butshould still be the same as the values of the corresponding portions ofthe following NRZ data. Thus, the slicing level may be set to themidpoint between the actual received base and peak values of the run-insignal in a known manner.

Starting with the last two cycles of the run-in signal, 9 μs of theoutput from the data slicer 30, representing the frame code, isillustrated on the CC SIG signal. When the CC SIG signal is greater thanthe illustrated slicing level of 25 IRE, the digital output signal fromthe slicer 30 is a logic ‘1’ signal, and when the CC SIG signal is lessthan the illustrated slicing level, the value of the digital outputsignal is a logic ‘0’ signal. The binary frame code produced by the dataslicer 30 in response to the CC SIG signal, therefore, is 101000011.

The microprocessor 50 supplies data specifying the line of the verticalblanking interval from which auxiliary digital data is to be extractedto the VBI data extractor 20 via the data bus and control signals. Thisdata may be stored in a register in the VBI data extractor 20 in a knownmanner.

The VBI data extractor 20 operates, in a manner described in more detailbelow, to process the digitized VBI signal from the VBI horizontal linepreviously specified by the microprocessor 50. The VBI data extractor 20determines the presence and format of, and extracts the data in the VBI.At the end of that VBI horizontal line, the microprocessor 50 isnotified by means of an interrupt request on the IRQ output terminal. Inresponse to the interrupt request, the microprocessor 50 determines ifVBI data was present in that line, and if so, transfers the extracteddata from the VBI data extractor 20 to the microprocessor via the databus by means of read enable signals supplied to the VBI data extractor20 via the control output terminal, all as described in more detailbelow.

FIG. 3 is a more detailed block diagram of a vertical blanking intervaldata extractor 20 according to the present invention. In FIG. 3, aninput terminal V receives the digitized VBI component of the videosignal from the data slicer 30 (of FIG. 2). The input terminal V iscoupled to a serial data input terminal SI of a 32 bit shift register204. A 32 bit parallel output terminal PO of the shift register 204 iscoupled to respective input terminals of a parity generator 206, a framecode detector 208 and a latch 210. A four bit output terminal of theparity generator 206 is coupled to a corresponding input terminal of thelatch 210.

First and second output terminals of the frame code detector 208,producing respective signals CC FRAME and GS FRAME (described in moredetail below), are coupled to corresponding input terminals of acontroller circuit 212. An input terminal S, receives the compositesynchronization signal from the synchronization signal separator 10 (ofFIG. 2). The input terminal S is coupled to a corresponding inputterminal of the controller circuit 212. The 4 Mhz clock signal from thecrystal oscillator 40 (of FIG. 2) is coupled to a clock signal inputterminal of the controller circuit 212.

A first output terminal of the controller circuit 212, producing a shiftclock signal is coupled to a shift clock input terminal of the shiftregister 204. Second and third output terminals of the controllercircuit 212, producing signals GS MODE and CC MODE, respectively,(described in more detail below), are coupled to corresponding inputterminals of the latch 210. A fourth output terminal of the controllercircuit 212, producing a LINE signal, is coupled to a clock inputterminal CLK of the latch 210.

A fifth output terminal of the controller circuit 212, producing aninterrupt request signal IRQ, is coupled to an output terminal IRQ,which is coupled to the microprocessor 50 (of FIG. 2). A CNTRL inputterminal is coupled to a control output terminal of the microprocessor50. The CNTRL input terminal is coupled to a corresponding inputterminal of the controller circuit 212, and to five enable inputterminals: ENB 1, ENB 2, ENB 3, ENB 4 and ENB S of a latch 210. Aneight-bit bidirectional data bus terminal is also coupled to themicroprocessor 50. The data bus terminal is coupled to an input terminalof the controller circuit 212 and to five eight-bit data outputterminals: DO 1, DO 2, DO 3, DO 4 and DO 5 of the latch 210.

In general operation, the microprocessor 50 (of FIG. 2) transfers dataspecifying a horizontal line in the vertical blanking interval to aregister REG in the controller circuit 212, via the data bus and controlsignals at the CNTRL input terminal, in a known manner. The controllercircuit 212 monitors the composite synchronization signal from the 5input terminal. When the horizontal line specified in the register REGoccurs, the VBI signal serial data stream for that horizontal line, fromthe data slicer 30, is shifted through the shift register 204 inresponse to the shift clock signal from the controller circuit 212. Theframe code detector 208 monitors the 32 bits at the parallel outputterminal of the shift register 204 to detect the frame code of either aclosed caption format signal or a Gemstar format signal.

If a closed caption format signal is detected, an indication that closedcaption format data is available is supplied to the latch 210 via the CCMODE signal. If a Gemstar format signal is detected, an indication thatGemstar format data is available is supplied to the latch 210 via the GSMODE signal. In either of these cases, the auxiliary digital data in thedetected format is extracted by the shift register 204 and, along withassociated parity information from the parity generator 206, also storedin the latch 210. If neither format signal is detected, an indicationthat no data is available is stored in the latch 210. At the same timethe above information is stored in the latch 210, an interrupt signal issupplied to the microprocessor 50 via the IRQ signal line. Themicroprocessor 50, in response to the interrupt request signal, readsthe contents of the latch 210, via the data bus and enable signals onthe CNTRL input terminal, all in a manner to be described in more detailbelow.

Although the illustrated embodiment includes the latch 210, one skilledin the art will understand that it is not absolutely required. If themicroprocessor 50 can respond to the IRQ signal, and retrieve the GSMODE and CC MODE signals, and the auxiliary digital data and associatedparity data before the next occurrence of the particular VBI lineinterval (the VBI line interval specified by data in register REG inFIG. 3), then the latch 210 may be omitted. In this case, themicroprocessor 50 reads the data directly from controller circuit 212,the shift register 204 and parity generator 206.

The controller circuit 212 includes counters and associated circuitry(not shown), of a known arrangement, for monitoring the compositesynchronization signal from the S input terminal to detect verticalfields and count horizontal lines. The controller circuit 212 alsoincludes circuitry, also of known arrangement, to compare the currenthorizontal line to the horizontal line specified by the data in theregister REG. The LINE signal is made active (e.g., a logic ‘1’ as inthe illustrated embodiment) at the beginning of the ‘active portion’ ofthe specified horizontal line, and remains inactive (logic ‘0’)otherwise. Referring to FIG. 1, the topmost waveform illustrates theLINE signal for the horizontal line in the vertical blanking intervalspecified by the data in the register REG.

At the same time the LINE signal is made active, the controller circuit212 begins to supply a 4 Mhz shift clock to the shift register 204. Inthis manner, the serial bit stream from the data slicer 30 (of FIG. 2),representing the VBI video signal, is clocked through the shift register204. In the illustrated embodiment, the shift register 204 is clocked atthe leading edges of the shift clock signal. As described above, the VBIdata signal has the format illustrated in either the CC SIG waveform orthe GS SIG waveform of FIG. 1. The Gemstar format signal GS SIG, afteran initial 10.5 μs period and a five cycle run-in clock period, isfollowed by a 9 μs interval which, when digitized, contains a frame codesignal which has the digital value 011101101. During the same 9 μs timeinterval, the closed caption format signal CC SIG includes a digital bitstream which has the value 101000011.

In the illustrated embodiment, the frame code interval is the 9 μsinterval following the initial 10.5 μs period and five cycle run-inclock period, which is common to both format signals. That is, the framecode interval starts at the first point where the two different formatsignals have different values, and ends where the digital auxiliary datafor both format signals starts. One skilled in the art will understandthat the definition of a frame code period is arbitrary and can includeany portion of the signal which is sufficient to distinguish data in oneformat from data in the other format.

The frame code detector 208 monitors the state of the 32 bits at theparallel output terminal of the shift register 204. The frame codedetector 208 operates in one of two operating modes. The first mode is asearch mode during which the detector searches for any occurrence ofauxiliary information such as a frame code. That is, in the search mode,it is not 5 known whether auxiliary digital data in either closedcaption or Gemstar format is included in the video signal, and if it is,it is not known what line contains that data. Such data could beincluded in any horizontal line in the vertical blanking interval: forexample, from line 10 to 20 in either field 1 or 2. Furthermore, it ispossible that data in other formats is inserted into lines in thevertical blanking interval. To increase certainty of detection andminimize false identification of an arbitrary signal as the desiredformat signal, the criteria for detecting either the closed caption orGemstar frame code are tightened in the search mode. All available framecode bits in the received digitized VBI signal are compared tocorresponding bits in either the Gemstar, frame code of 011110110 or theclosed caption frame code of 1010000011, possibly for more than onesequential frame of video during the search mode. Once the presence andlocation of auxiliary digital data in either closed caption or Gemstarformat has been verified, the search mode is terminated.

When the search mode is terminated, the frame code detector 208 entersthe second mode of operation, termed the locked-on mode in the remainderof this application, during which a particular occurrence of auxiliaryinformation is detected. That is, in the locked-on mode, the location ofthe auxiliary data in the vertical blanking interval has beendetermined, and data representing that location is stored in theregister PEG in the controller circuit 112.

Thus, the detector can look for occurrence of the desired auxiliaryinformation in the particular line interval that is indicated by thedata stored in register REG. The frame code detector 208, in a manner tobe described in more detail below, continues to monitor the 32 bits fromthe shift register 204 to detect either the Gemstar frame code of01110110 or the closed caption frame code of 101000011. In the locked-onmode, however, in order to minimize disruption in the presence of anoisy signal, the detection criteria for detecting either the closedcaption or Gemstar frame codes are loosened relative to those in thesearch mode. The remainder of this application will describe thelocked-on mode of operation, unless the search mode is explicitlyspecified.

Whenever the Gemstar frame code of 011101101 is detected by the framecode detector 208, a GS FRAME pulse signal, as illustrated in FIG. 1, isgenerated. In a similar manner, although not illustrated in FIG. 1,whenever the closed caption frame code of 101000011 is detected by theframe code detector 208, a CC FRAME pulse signal is generated, all in amanner to be described in more detail below.

The controller circuit 212 receives the CC FRAME and GS FRAME signalsfrom the frame code detector 208. In order to increase the accuracy ofdetection of the frame code, the controller circuit 212 generates aFRAME WINDOW signal. The FRAME WINDOW signal is derived from thecomposite synchronization signal, in a known manner, and is made active(is a logic ‘1’ signal in the illustrated embodiment) for a timeinterval surrounding the nominal time when either a GS FRAME or CC FRAMEpulse could occur validly and is inactive (logic ‘0’) otherwise. In theillustrated embodiment, the FRAME WINDOW signal is active for a 5 μsinterval around the nominal time when a GS FRAME or CC FRAME pulseshould occur, which is 29.5 μs from the time the LINE signal becomeactive. This is illustrated as waveform FRAME WINDOW in FIG. 1.

During the time interval when the FRAME WINDOW signal is active, the CCFRAME and GS FRAME signals are monitored by the controller circuit 212.If a pulse is detected in the GS FRAME signal (as illustrated in the GSFRAME signal in FIG. 1), the controller circuit 212 makes the GS MODEsignal active (logic ‘1’ in the illustrated embodiment) as illustratedin the GS MODE signal in FIG. 1. This indicates that Gemstar format datais present in the specified horizontal line, and that data follows. TheGemstar format data is in the form of a 32 bit NRZ data stream, each bitinterval being 1 μs, as described above. In response to the detection ofthe GS FRAME signal, the controller circuit 212 supplies a shift clocksignal to the shift register 204 such that sampling signals (e.g.leading edges) are generated at the middle of each Gemstar data bitinterval as illustrated in the GS SAMPLE CLOCK signal in FIG. 1. Thus,for the first portion of the line. e.g. until the GS FRAME pulse isdetected, the shift clock signal is a 4 MHz clock signal. For the secondportion of the line. e.g. after the GS FRAME pulse is detected, theshift clock signal is a 1 MHz signal phased so that leading edges (e.g.sampling signals) are synchronized to the center of the Gemstar data bitintervals.

In a similar manner, although not illustrated in FIG. 1, if a pulse isdetected in the CC FRAME signal, the controller circuit 212 makes the CCMODE signal active (logic ‘1’ in the illustrated embodiment). Thisindicates that closed caption format is present in the specifiedhorizontal line, and that data follows. The closed caption format datais in the form of a 16 bit NRZ data stream, each bit interval being 2μs. In response to the detection of the CC FRAME signal, the controllercircuit 212 supplies a shift clock signal to the shift register 204 suchthat sampling signals (e.g. leading edges) are generated at the middleof each closed caption data bit period, as illustrated in the CC SAMPLECLOCK signal in FIG. 1. Thus, for the first portion of the line, e.g.until the CC FRAME pulse is detected, the shift clock signal is a 4 MHzclock signal. For the second portion of the line, e.g. after the CCFRAME pulse is detected, the shift clock signal is a 500 kHz signalphased so that leading edges (e.g. sampling signals) are synchronized tothe center of the closed caption data bit intervals.

If neither a CC FRAME signal nor a GS FRAME signal is detected by theframe code detector 208 while the FRAME WINDOW signal is active, thenneither the GS MODE nor the CC MODE signal is generated, and no changeof frequency and phase in the shift clock signal occurs.

In response to the changed shift clock signal, the shift register 204samples the digital signal from the data slicer 30 (of FIG. 2) at themiddle of the bit intervals for either the Gemstar format (GS SIG ofFIG. 1) or the closed caption format (CC SIG), as selected by the CCFRAME and GS FRAME signals. At the end of the active portion of the VBIhorizontal line, the shift register 204 contains the VBI data. This datais present at the parallel output terminal PO of the shift register 204,and supplied to the latch 210. The 32 bits are partitioned into 4eight-bit bytes. Simultaneously, the parity generator 206 calculatesfour parity bits, one corresponding to each of the partitioned bytesfrom the shift register 204. The parity bits are also supplied to thelatch 210.

When the active portion of the VBI horizontal line ends, the LINE signalis made inactive again by the controller circuit 212, as illustrated inFIG. 1. The LINE signal is coupled to the clock input terminal CLK ofthe latch 210. In response to the LINE signal becoming inactive, thelatch 210 latches the VBI data signals from the shift register 204, theGS MODE and CC MODE signals from the controller circuit 212, and theparity bits from the parity generator 206. The four bytes from the shiftregister 204 are latched into respective four bytes of the latch 210.The four parity bits are latched into four bits of a fifth byte, termedthe status byte, of the latch 210. Finally, the GS MODE and CC MODEsignals from the controller circuit 212 are latched into fifth and sixthbits of the fifth, status, byte in the latch 210.

Also in response to the LINE signal becoming inactive, and simultaneouswith latching the data and status information into the latch 210, thecontroller circuit 212 generates an interrupt request signal IRQ, whichis supplied to the microprocessor 50 (of FIG. 2). In a known manner, inresponse to the IRQ signal, the microprocessor 50 executes an interrupthandler routine. The interrupt handler routine conditions themicroprocessor 50 to read the status byte from the latch 210 byactivating the status byte enable signal ENB S. In response to thestatus byte enable signal ENB S, the output terminal of the latch 210producing the status byte, DO S is coupled to the microprocessor 50 databus, and the data is read by the microprocessor 50. The interrupthandler tests the data bits containing the GS MODE and CC MODE signals.If the GS MODE bit is active, then 32 bits of auxiliary digital datawere transmitted in the VBI line, and all four data bytes are read bythe microprocessor 50. In this case, the microprocessor sequentiallyactivates the data byte enable signals ENB 1. ENB 2. ENB 3 and ENB 4. Inresponse to the ENB 1 signal, the latch 210 places the contents of thefirst data byte at data output terminal DO 1 on the data bus, and thatdata is read by the microprocessor 50. Similarly, the second, third andfourth bytes, at data output terminals DO 2, DO 3 and DO 4,respectively, are placed on the data bus in response to data byte enablesignals ENB 2, ENB 3 and ENB 4, respectively. If desired, themicroprocessor 50 can also check the parity of these data bytes byanalyzing the four parity bits present in the status byte.

In the event that the CC MODE signal is active, this indicates thatclosed captioning information was transmitted during the VBI line. Inthis case, however, only 16 bits, or two bytes of auxiliary digital datawere transmitted, and only data bytes at the data output terminals DO 3and DO 4 contain valid information. The microprocessor reads these databytes after providing the respective enable signals. The received databytes can then be processed in the appropriate manner, such asextracting scheduling information and displaying such information to theviewer.

FIG. 4 is a more detailed diagram, partially in block form, andpartially in logic form, illustrating the portion of the frame codedetector 208 operative during the locked-on mode. In FIG. 4, elementswhich are the same as those illustrated in FIG. 3 are designated by thesame reference number and are not described in detail. In FIG. 4, theshift register 204 is illustrated with the serial input terminal SI andthe shift clock input terminal CLK, and with 32 single-bit paralleloutput terminals. The leftmost output terminal, labeled “0” contains themost recently received bit.

Respective output terminals 0 and 4 are coupled to first and secondinput terminals of a negative output AND (NAND) gate 302. Respectiveoutput terminals 8, 12 and 16 are coupled to first, second and thirdinput terminals of a negative output OR (NOR) gate 304. Respectiveoutput terminals 8, 12, 20 and 28 are coupled to first, second, thirdand fourth input terminals of a second NAND gate 306. Output terminal 4is coupled to a first input terminal of a second NOR gate 308. An outputterminal of the first NAND gate 302 is coupled to a fourth inputterminal of the NOR gate 304, and an output terminal of the second NANDgate 306 is coupled to a second input terminal of the second NOR gate308. An output terminal of the first NOR gate 304 produces the CC FRAMEsignal, and an output terminal of the second NOR gate 308 produces theGS FRAME signal.

Referring to FIG. 1, up to the point where either a GS FRAME signal or aCC FRAME signal is generated, the digital bit stream from the slicer 10(of FIG. 2) is sampled at a 4 Mhz rate in response to the GS SAMPLECLOCK signal. Because each bit in the frame code portion of the signalis 1 μs in duration, each such bit is oversampled four times by theshift register 204. That is, each bit is stored in four adjacentlocations in the shift register 204. Thus, in order to properly samplethe different bits in the frame code, every fourth bit in the shiftregister 204 is processed by the frame code detector.

In the current embodiment, only eight of the nine frame code bits may bestored in the 32 bit shift register 204, consequently only those eightbits are available for processing to detect a valid Gemstar or closedcaption frame code. However, in the illustrated embodiment only a subsetof 5 bits of the available set of eight bits are processed to determinewhether a closed caption frame or a Gemstar frame is present. Those fivebits, and their values, are: (x)xxx00011 to detect a valid closedcaption frame code, and (x)1x1x110x to detect a valid Gemstar framecode, where (x) indicates the ninth, unavailable bit, and x indicates a‘don't care’ bit.

In FIG. 4, the leftmost bits of the frame code arrive at the shiftregister 204 first, and are shifted out first. Thus, the first bit ofthe frame code is shifted completely through and out of the shiftregister 204 before the last bit is received. Conversely, the last bitof the frame code (rightmost bit) is the most recent bit shifted intothe shift register 204 and is in the leftmost bit position (bit 0) inthe shift register 204 as it is illustrated in FIG. 4.

In FIG. 4, if both shift register 204 bits 0 and 4, representing therightmost two bits of the frame code, are logic ‘1’ bits, then theoutput of the first NAND gate 302 is a logic ‘0’ signal, otherwise it isa logic ‘1’ signal. If shift register 204 bits 8, 12 and 16,representing the next three bits of the frame code, and the output fromthe first NAND gate 302, are all logic ‘0’ signals, then the signal atthe output terminal of the first NOR ate 304, CC FRAME, is a logic ‘1’signal indicating that a closed caption frame code has been detected.

If bits 8, 12, 20 and 28 from the shift resister 204 are all logic ‘1’signals, then the output from the second NAND gate 306 is a logic ‘0’signal. If bit 4 from the shift register 204 and the output of thesecond NAND gate 306 are both logic ‘0’ signals, then the signal at theoutput terminal of the second NOR gate 308, GS FRAME, is a logic ‘1’signal indicating that a Gemstar frame code has been detected. Becausethe frame code bits are each 1 microsecond in duration and areoversampled by the 4 MHz clock (i.e., 4 successive samples of each framecode bit are stored in the shift register), the GS FRAME signal remainsvalid for four shift clock cycles.

The particular subset of five bits selected for use by the frame codedetectors of the present invention have been selected on the basis ofexperiments made with the objective to maximize detection of valid framecodes in weak signal condition, which is equivalent to signalscontaining random, or white noise (correlated noise may produce otherresults). By implementing the frame code detectors as illustrated, onlya few relatively simple gates are required, while performance issubstantially equivalent to detectors that process all frame code bits.Implementing frame code detectors that process all frame code bits,however, would require a larger shift register (44 shift register bitsto hold all 11 frame code bits of the Gamester frame code), and asubstantially more complicated combinatorial logic circuit to processthose eleven bits (eight bits for the closed caption frame code).

FIG. 5 is a more detailed diagram, partially in block form, andpartially in logic form, illustrating a portion of the controllercircuit 212 illustrated in FIG. 3 which generates the GS MODE and CCMODE signals in response to the GS FRAME and CC FRAME signals,respectively. In FIG. 5, the 4 MHz clock signal from the crystaloscillator 40 (of FIG. 2) is coupled to an input terminal of an inverter402. An output terminal of the inverter 402 is coupled to respectiveclock input terminals of a first D flip flop 404 and a second D flipflop 406, and to a first input terminal of a closed caption (CC) framedetector circuit 420. The FRAME WINDOW signal, generated internally fromthe composite synchronization signal, as described above, is coupled toa first input terminal of an AND gate 408 an a second input terminal ofthe CC frame detector 420.

The GS FRAME signal from the frame code detector 208 (of FIG. 3) iscoupled to a second input terminal of the AND gate 408. An outputterminal of the AND gate is coupled to a D input terminal of the first Dflip flop 404 and a first input terminal of a first NAND gate 410. A Qoutput terminal of the first flip flop 404 is coupled to a second inputterminal of the first NAND gate 410. An output terminal of the firstNAND gate is coupled to a first input terminal of a second NAND gate412. An output terminal of the second NAND gate 412 is coupled to a Dinput terminal of the second flip flop 406. A Q output terminal of thesecond flip flop 406 generates the GS MODE signal which is coupled tothe latch 210. The Q output terminal of the second flip flop 406 is alsocoupled to an input terminal of a second inverter 414. An outputterminal of the second inverter 414 is coupled to a second inputterminal of the second NAND gate 412. The combination of the AND gate408, first D flip flop 404, second D flip flop 406, first NAND gate 410,second NAND gate 412 and inverter 414 form a Gemstar (GS) framedetector.

The CC FRAME signal from the frame code detector 208 (of FIG. 3) iscoupled to a third input terminal of the CC frame detector 420. The CCframe detector 420 is constructed identically to the GS frame detector416, and operates in the same manner (described in more detail below).An output terminal of the CC FRAME detector produces the CC MODE nosignal, and is coupled to the latch 210.

In operation, at the beginning of each horizontal line, the first andsecond D flip flops 404 and 406 are reset, by circuitry of a knowndesign (not shown), e.g., generating a reset signal in response to thehorizontal synchronization component in the composite video signal andsupplying that reset signal to a reset input (not shown in FIG. 5) ofeach of flip flops 404 and 406. Consequently, the signals at the Qoutput terminals of the first and second D flip flops 404 and 406 at thebeginning of a horizontal line are both logic ‘0’ signals. Thus, the GSMODE output signal is a logic ‘0’ signal. In addition, the GS FRAMEinput signal is a logic ‘0’ signal until a Gemstar frame code isdetected, (as illustrated in FIG. 1). So long as the FRAME WINDOW signalremains a logic ‘0’ signal, the AND gate 408 remains disabled, andproduces a logic ‘0’ signal, causing Q output terminal of the first Dflip flop 404 to continue to produce a logic ‘0’ signal when clocked bythe inserted 4 MHz clock signal. The first NAND gate 410 is therebydisabled and generates a logic ‘1’ signal. The output of the inverter414, similarly is a logic ‘1’ signal. The output of the second NAND gate412, thus, is a logic ‘0’signal causing the second D flip flop 406 tocontinue to produce a logic ‘0’ signal at its Q output terminal whenclocked by the inverted 4 MHz clock signal. The GS frame detector 416remains in this state so long as no GS FRAME signal pulse is received.

The GS frame detector 416 recognizes receipt of a valid Gemstar framecode only if that code occurs in two successive cycles of the 4 MHzclock signal. (A valid frame code signal should be available for foursuccessive cycles of the 4 MHz clock because of the oversampling of the1 microsecond frame code bits by the 4 MHz clock as explained above.)This improves the accuracy of the frame code detection process. The ANDgate 408 is enabled when the FRAME WINDOW signal, which defines a timewindow within which a valid frame code may occur, becomes active (asillustrated in FIG. 1). While the FRAME WINDOW signal is active, anypulse on the GS FRAME signal will be passed through the AND gate 408.Otherwise, the AND gate 408 remains disabled, produces a logic ‘0’signal at its output terminal.

If a logic 1’ pulse occurs on the GS FRAME signal while the FRAME WINDOWsignal is active, a logic ‘1’ is supplied to the D input terminal of thefirst flip flop 404. The first D flip flop 404 is clocked by theinverted 4 MHz clock signal, i.e. a clock signal which is delayed byone-half cycle compared to the 4 MHz clock signal. When the first D flipflop 404 is clocked, a logic ‘1’ signal appears at its Q outputterminal. This enables the first NAND gate 410.

If the GS FRAME signal remains a logic ‘1’ signal for the nextsucceeding cycle of the 4 MHz clock signal, the GS FRAME signalconditions the first NAND gate 410 to produce a logic ‘0’ signal.Because the Q output terminal of the second flip flop 406 is still alogic ‘0’ signal, the output terminal of the inverter 414 produces alogic ‘1’ signal. However, the logic ‘0’ signal from the first NAND gate410 conditions the second NAND gate 412 to produce a logic ‘1’ signal atits output terminal. This logic ‘1’ signal is clocked through the secondflip flop 406 at the next cycle of the inverted 4 MHz clock signal. TheQ output terminal of the second flip flop 406, and thus the GS MODEsignal, is made a logic ‘1’ signal, as illustrated in FIG. 1. The logic‘1’ signal at the output of the second flip flop 406 conditions theinverter 414 to generate a logic ‘0’ signal at its output terminal. Thisdisables the second NAND (ate 412, which in turn produces a logic ‘1’signal. This causes the second flip flop 406 to continue to produce alogic ‘1’ GS MODE signal when clocked by the inverted 4 MHz clocksignal. Thus, when a GS FRAME signal is detected for two consecutive 4MHz clock signal cycles, the GS MODE signal is made active, and remainsactive until reset at the beginning of the next horizontal line, asdescribed above.

If, however, the GS FRAME signal does not remain a logic ‘1’ signal atthe next succeeding cycle of the 4 MHz clock signal, the AND gate 408produces a logic ‘0’ signal, which returns the first flip flop 404 toits quiescent condition, i.e. the Q output terminal generates a logic‘0’ signal. Thus, the first NAND gate 410 is disabled and produces alogic ‘1’ signal. This conditions the second NAND gate 412 to produce alogic ‘0’ signal, which in turn, maintains the second flip flop 406 inits quiescent condition, i.e. the Q output terminal generates a logic‘0’ signal. Thus, the GS MODE signal remains a logic ‘0’ if the GS FRAMEsignal is active for only one 4 MHz clock cycle.

As described above, the CC FRAME detector 420 is constructed identicallyto the GS FRAME detector 416 and operates in the same manner to generatea logic ‘1’ CC MODE signal when the CC FRAME signal is present for twoconsecutive 4 MHz clock cycles when the FRAME WINDOW signal is active.The CC MODE signal then remains a logic ‘1’ signal until the beginningof the next horizontal line.

FIG. 6 shows, partially in block form, and partially in logic form,aportion of the controller circuit 212 of FIG. 3 which controls the SHIFTCLOCK signal supplied to the shift register 204. In FIG. 6, the LINEsignal, generated internally in response to the compositesynchronization signal, as described above, is coupled to a first inputterminal of a first inverted input OR gate 502 and an input terminal ofan inverter 504. An output terminal of the inverter 504 is coupled to afirst input terminal of a NOR gate 506 and to the interrupt requestsignal output terminal IRQ, which is coupled to the microprocessor 50(of FIG. 2).

The 4 Mhz clock signal from the crystal oscillator 40 (of FIG. 2) iscoupled to an input terminal of a counter 508, to a clock input terminalof a D flip flop 510, and to a first input terminal of a first NAND gate512. A first output terminal of the counter 508 generates a Gemstarclocking signal (GS CLOCK) that is coupled to a first input terminal ofa second NAND gate 514. A second output terminal of the counter 508generates a closed caption clocking signal (CC CLOCK) that is coupled toa first input terminal of a third NAND gate 516. An output terminal ofthe first NAND Pate 512 is coupled to a first input terminal of a secondinverted input OR gate 518; an output terminal of the second NAND gate514 is coupled to a second input terminal of the second OR gate 518; andan output terminal of the third NAND gate 516 is coupled to a thirdinput terminal of the second OR gate 518. An output terminal of thesecond OR gate produces the SHIFT CLOCK signal, which is coupled to theclock input terminal of the shift register 204 (of FIG. 3). Incombination, the NOR gate 506; first, second, and third NAND gates 512,514 and 516; and the second OR gate 518 form a multiplexer 560.

The GS MODE signal from the mode signal control circuitry illustrated inFIG. 5 is coupled to a second input terminal of the NOR gate 506, to afirst input terminal of a third OR gate 520, and to a second inputterminal of the second NAND gate 514. The CC MODE signal from the modesignal control circuitry is coupled to a third input terminal of the NORgate 506, to a second input terminal of the third OR gate 520, and to asecond input terminal of the third NAND gate 516. An output terminal ofthe NOR gate 506, generating a FAST CLOCK signal, as illustrated in FIG.1, is coupled to a second input terminal of the first NAND gate 512.

An output terminal of the third OR gate 520 is coupled to a D inputterminal of the D flip flop 510, and to a first input terminal of afourth NAND gate 522. A Q output terminal of the D flip flop 510 iscoupled to an input terminal of a second inverter 524. An outputterminal of the second inverter 524 is coupled to a second inputterminal of the fourth NAND gate 522. In combination, the third OR gate520, the D flip flop 510, the second inverter 524 and the fourth NANDgate 522 form a counter reset circuit 550. An output terminal of thefourth NAND gate 522 is coupled to a second input terminal of the firstOR gate 502. An output terminal of the first OR sate 502 is coupled to areset input terminal R of the counter 508.

In operation, the shift register 204 (of FIG. 3) is clocked at one ofthree rates during the active portion of the VBI horizontal linespecified by the data in the register REG in the controller circuit 212:at a fast clock rate of 4 MHz before a valid frame code is detected, ata Gemstar data rate of 1 MHz after a Gemstar frame code is detected, andat a closed caption data rate of 500 kHz after a closed caption framecode is detected. The counter 508 receives the 4 MHz clock signal and,in a known manner, for example, using flip flop divider stages,frequency divides the 4 MHz clock signal to generate a 1 MHz Gemstarclocking signal GS CLOCK, and a 500 kHz closed caption clocking signalCC CLOCK. The 4 MHz clock signal, the GS CLOCK signal and the CC CLOCKsignal are supplied to data input terminals of the multiplexer 560. Themultiplexer 560 is controlled by the inverted LINE signal, the GS MODEsignal and the CC MODE signal to generate a SHIFT CLOCK signal at theappropriate frequency.

As described above, and illustrated in FIG. 1, the LINE, GS MODE and CCMODE signals are logic ‘0’ signals at the beginning of each horizontalline. In response to a logic ‘0’LINE signal, the first OR gate 502provides a logic ‘1’ signal to the reset input terminal R of the counter508, which remains in the reset state. The LINE signal is made a logic‘1’ signal during the active portion of the VBI horizontal linespecified by the data in the register REG in the controller circuit 212.In response to a logic ‘1’ LINE signal the first OR gate 502 provides alogic ‘0’ signal to the reset input terminal R of the counter 508, whichbegins to operate normally.

The LINE signal is inverted by the first inverter 504. The inverted LINEsignal, thus, is a logic ‘0’ signal during the active portion of the VBIhorizontal line specified by the data in the register REG, and a logic‘1’ otherwise. Thus at the beginning of the active portion of thespecified line, all of the inverted LINE, GS MODE and CC MODE signalsare logic ‘0’. In response to all of the inverted LINE, GS MODE and CCMODE signals being logic ‘0’ signals, the NOR gate 506 generates a logic‘1’ signal, which enables the first NAND gate 512. When enabled, thefirst NAND gate 512 passes the 4 MHz clock signal to its output terminalSimultaneously, in response to the GS MODE signal being a logic ‘0’, thesecond NAND rate 514 is disabled which blocks the GS CLOCK signal fromthe second OR gate 518, and in response to the CC MODE signal being alogic ‘0’ signal, the third NAND gate 516 is disabled which blocks theCC CLOCK signal from the second OR gate 518 The second OR gate 518passes the 4 MHz signal to its output terminal, which, in turn, iscoupled to the clock input terminal of the shift register 204. Thus, atthe beginning of the active portion of the specified horizontal line,the shift clock is a 4 MHz signal.

If neither a Gemstar or closed caption frame code is detected in thespecified horizontal line, the shift clock signal control circuitry ofFIG. 6 remains in this state until the end of the active portion of theline. At the end of the active portion of the line, the LINE signalbecomes a logic ‘0’ signal and the inverted LINE signal becomes a logic‘1’ signal. The logic ‘0’ LINE signal places the counter 508 into thereset state, as described above. The logic ‘1’ inverted LINE signalconditions the NOR gate 506 to produce a logic ‘0’ signal at its outputterminal, which disables the first NAND gate 512, blocking the 4 MHzsignal from the second OR gate 518 and the clock input terminal of theshift register 204.

When a Gemstar frame code is detected, the GS MODE signal becomes alogic ‘1’ signal, as described above and illustrated in FIGS. 4 and 5.In response to a logic ‘1’ GS MODE signal, the NOR gate 506 generates alogic ‘0’ signal at its output terminal, disabling the first NAND gate512, and blocking the 4 MHz signal from the second OR gate 518.Simultaneously, the logic ‘1’ GS MODE signal enables the second NANDgate 514, which passes the GS CLOCK signal from the counter 508 to thesecond OR gate 518, and to the clock input terminal of the shiftregister 204. The resulting waveform is illustrated in FIG. 1 as the GSSAMPLE CLOCK waveform.

If a closed caption frame code is detected, the CC MODE signal becomes alogic ‘1’ signal. In response to a logic ‘1’ CC MODE signal, the NORgate 506 generates a logic ‘0’ signal at its output terminal, disablingthe first NAND gate 512, and blocking the 4 MHz signal from the secondOR gate 518. Simultaneously, the logic ‘1’ CC MODE signal enables thethird NAND gate 516, which passes the CC CLOCK signal from the counter508 to the second OR gate 518, and to the clock input terminal of theshift register 204. The resulting, waveform is illustrated in FIG. 1 asthe CC SAMPLE CLOCK waveform.

In order to adjust the phase of the shift register 204 clock to thecenter of the data bit periods, the counter 508 is reset when either theGS MODE or CC MODE signals become a logic ‘1’ signal. At the beginningof each horizontal line the GS MODE or CC MODE signals are both logic‘0’ signals. This causes the third OR gate 520 to produce a logic ‘0’signal. This logic ‘0’ signal is applied to the fourth NAND gate 522,disabling the NAND gate 522, which generates a logic ‘1’ COUNTER RESETsignal. At the same time, the logic ‘0’ signal at the output terminal ofthe third OR gate 520 is clocked through the D flip flop 510 at each 4MHz clock cycle to the Q output terminal. The logic ‘0’ signal at the Qoutput terminal of the flip flop 510 is inverted by the second inverter524 which provides a logic ‘1’ input signal to the (disabled) fourthNAND gate 522.

The logic ‘1’ COUNTER RESET signal from the fourth NAND gate 522 issupplied to the first OR gate 502. In response to this logic ‘1’ signal,the first OR gate 502 provides a logic ‘0’ signal to the reset inputterminal R to the counter 508. In response to a logic ‘0’ reset signal,the counter 508 operates normally.

When either of the GS MODE or CC MODE signals become a logic ‘1’, thethird OR gate 520 produces a logic ‘1’ signal at its output terminal.This signal enables the fourth NAND gate 522. The enabled fourth NANDgate 522 produces a logic ‘0’ signal at its output terminal as theCOUNTER RESET signal in response to the logic ‘1’ signal from the secondinverter 524. The logic ‘0’ COUNTER RESET signal conditions the first ORgate 502 to provide a logic ‘1’ signal to the reset input terminal R ofthe counter 508, which enters the reset state.

At the next 4 MHz clock cycle, the logic ‘1’ signal from the third ORgate 520 is latched through the D flip flop 510, and appears at its Qoutput terminal. This logic ‘1’ signal is inverted by the secondinverter 524, which supplies a logic ‘0’ signal to the fourth NAND gate522, disabling the fourth NAND gate again. The fourth NAND gate 522,thus, produces a logic ‘1’ signal again, conditioning the first OR gate502 to produce a logic ‘0’ signal and allowing the counter 508 tooperate normally again, but from a known, zeroed, state. Consequently,the counter will produce GS CLOCK and CC CLOCK signals with samplingtimes (i.e. leading edges) properly aligned with the middle of therespective Gemstar and closed caption data bit intervals.

Although the illustrated embodiment is described for Gemstar and closedcaption data, one skilled in the art will understand that the presentinvention can be used in any data transmission system in which a framecode can be used to identify the format of the following auxiliarydigital data.

What is claimed is:
 1. In a television receiver, an auxiliary digitaldata extractor comprising: a source of a composite video signalincluding an auxiliary digital data component comprising one of: a) afirst frame code having a predetermined number of bits and auxiliarydata in a first format, and b) a second frame code having thepredetermined number of bits and auxiliary data in a second format;comprising: a frame code detector, coupled to the composite video signalsource, and responsive to a first proper subset of the predeterminednumber of frame code bits for detecting the first frame code, andresponsive to a second proper subset of the predetermined number offrame code bits for detecting the second frame code; an auxiliary datautilization circuit, coupled to the composite video signal source andthe frame code detector, for selectively receiving auxiliary data in thefirst format in response to detection of the first frame code and in thesecond format in response to detection of the second frame code.
 2. Thereceiver of claim 1 further comprising: a slicer, coupled to thecomposite video signal source, for generating a digital bit streamrepresenting the composite video signal; a register, coupled to theslicer, responsive to a clocking signal, and having an output terminalgenerating the predetermined number of bits, for storing samples of thedigital bit stream from the slicer; and a register controller, coupledto the frame code detector, and having an output terminal producing theclocking signal for the register, for conditioning the register tosample the digital bit stream at a first rate when storing digital bitstream samples representing a frame code, at a second rate when storingsamples representing auxiliary data in the first format, and at a thirdrate when storing samples representing auxiliary data in the secondformat; wherein: the frame code detector is coupled to the register, andresponsive to a first subset of register output terminal bits,corresponding to the first subset of frame code bits, for detecting thefirst frame code, and responsive to a second subset of register outputterminal bits, corresponding to the second subset of frame code bits,for detecting the second frame code.
 3. The receiver of claim 2 wherein:the register controller comprises circuitry for venerating a registerclocking signal for the register at the first rate such that theregister is conditioned to oversample the composite video signalrepresentative signal from the slicer when storing digital bit streamsamples representing the frame code; and the frame code detector furthercomprises circuitry to detect one of the first and second frame codeonly when the one of the first and second frame code is detected for twoconsecutive digital bit stream samples.
 4. The receiver of claim 2wherein the frame code detector comprises: a first combinatorial logiccircuit, coupled to the first subset of register output terminal bits,for generating a signal when signals at the first subset of registeroutput terminals correspond to the first frame code; and a secondcombinatorial logic circuit, coupled to the second subset of registeroutput terminal bits, for generating a signal when signals at the secondsubset of register output terminals correspond to the second frame code.5. The receiver of claim 2 wherein the auxiliary data utilizationcircuit is coupled to the register for receiving sampled auxiliary data.6. The receiver of claim 1 further comprising: a slicer, coupled to thecomposite video signal source, for generating a digital bit streamrepresenting the composite video signal; a register, coupled to theslicer, responsive to a clocking signal, and having an output terminalgenerating fewer than the predetermined number of frame code bits, forstoring samples of the digital bit stream from the slicer; and aregister controller, coupled to the frame code detector, and hashing anoutput terminal producing the clocking signal for the register, forconditioning the register to sample the digital bit stream at a firstrate when storing digital bit stream samples representing a frame code,at a second rate when storing samples representing auxiliary data in thefirst format, and at a third rate when storing samples representingauxiliary, data in the second format: wherein: the frame code detectoris coupled to the register, and responsive to a first subset of registeroutput terminal bits, corresponding to the first subset of frame codebits, for detecting the first frame code, and responsive to a secondsubset of register output terminal bits, corresponding to the secondsubset of frame code bits, for detecting the second frame code.
 7. Thereceiver of claim 6 wherein: the register controller comprises circuitryfor generating a register clocking signal for the register at the firstrate such that the register is conditioned to oversample the compositevideo signal representative signal from the slicer when storing digitalbit stream samples representing the frame code; and the frame codedetector further comprises circuitry to detect one of the first andsecond frame code only when the one of the first and second frame codeis detected for two consecutive digital bit stream samples.
 8. Thereceiver of claim 6 wherein the frame code detector comprises: a firstcombinatorial logic circuit, coupled to the first subset of registeroutput terminal bits, for generating a signal when signals at the firstsubset of register output terminals correspond to the first frame code;and a second combinatorial logic circuit, coupled to the second subsetof register output terminal bits, for generating a signal when signalsat the second subset of register output terminals correspond to thesecond frame code.
 9. The receiver of claim 6 wherein the auxiliary datautilization circuit is coupled to the register for receiving sampledauxiliary data.
 10. The receiver of claim 1 wherein the frame codedetector operates in a further search mode responsive to all of thepredetermined number of frame code bits for detecting one of the firstframe code and second frame code.
 11. The receiver of claim 1 whereinthe auxiliary digital data component is in the active portion of ahorizontal line in the vertical blanking interval composite videosignal.